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| AT93C46A Features * * * * * * * Low Voltage and Standard Voltage Operation 5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 2.5 (VCC = 2.5V to 5.5V) 3-Wire Serial Interface 2 MHz Clock Rate (5V) Compatibility Self-Timed Write Cycle (10 ms max) High Reliability Endurance: 1 Million Cycles Data Retention: 100 Years Automotive Grade and Extended Temperature Devices Available 8-Pin PDIP and JEDEC SOIC Packages Description The AT93C46A provides 1024 bits of serial electrically erasable programmable read only memory (EEPROM ) organized as 64 words of 16 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT93C46A is available in space saving 8-pin PDIP and 8-pin JEDEC packages. The AT93C46A is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought "high" following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. The AT93C46A is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V versions. 3-Wire Serial CMOS E2PROMs 1K (64 x 16) AT93C46A Pin Configurations Pin Name CS SK DI DO GND VCC NC DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply No Connect Don't Connect 8-Pin PDIP 8-Pin SOIC 0539A 2-79 Absolute Maximum Ratings* Operating Temperature................... -55C to +125C Storage Temperature...................... -65C to +150C Voltage on Any Pin with Respect to Ground ..................... -1.0V to +7.0V Maximum Operating Voltage ........................... 6.25V DC Output Current ......................................... 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram 2-80 AT93C46A AT93C46A Pin Capacitance (1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions COUT CIN Note: Max 5 5 Units pF pF Conditions VOUT = 0V VIN = 0V Output Capacitance (DO) Input Capacitance (CS, SK, DI) 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +2.5V to +5.5V, TAC = 0C to +70C, VCC = +2.5V to +5.5V (unless otherwise noted). Symbol VCC1 VCC2 VCC3 VCC4 ICC ISB1 ISB2 ISB3 IIL IOL VIL1 (1) VIH1 (1) VIL2 (1) VIH2 (1) VOL1 VOH1 VOL2 VOH2 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Condition Min 1.8 2.5 2.7 4.5 READ at 1.0 MHz WRITE at 1.0 MHz CS = 0V CS = 0V CS = 0V Typ Max 5.5 5.5 5.5 5.5 Units V V V V mA mA A A A A A V V V V V V VCC = 5.0V VCC = 2.5V VCC = 2.7V VCC = 5.0V VIN = 0V to VCC VIN = 0V to VCC 4.5V VCC 5.5V 1.8V VCC 2.7V 4.5V VCC 5.5V 1.8V VCC 2.7V 0.5 0.5 14.0 14.0 35.0 0.1 0.1 -0.1 2.0 0.0 VCC x 0.7 2.0 2.0 20.0 20.0 50.0 1.0 1.0 0.8 VCC + 1 VCC x 0.3 VCC + 1 0.4 IOL = 2.1 mA IOH = -0.4 mA IOL = 0.15 mA IOH = -100 A VCC - 0.2 2.4 0.2 1. VIL min and VIH max are reference only and are not tested. 2-81 AC Characteristics Applicable over recommended operating range from TA = -40C to + 85C, VCC = +2.5V to + 5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol fSK Parameter SK Clock Frequency Test Condition 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 4.5V VCC 2.7V VCC 2.5V VCC 1.8V VCC 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 0.1 4.5V VCC 5.5V 1 Min 0 0 0 0 250 250 500 1000 250 250 500 1000 250 250 500 1000 50 50 100 200 100 100 200 400 0 100 100 200 400 250 250 500 1000 250 250 500 1000 250 250 500 1000 100 100 200 400 10 Typ Max 2 1 0.5 0.25 Units MHz tSKH SK High Time ns tSKL SK Low Time ns tCS Minimum CS Low Time ns tCSS CS Setup Time Relative to SK ns tDIS tCSH tDIH DI Setup Time CS Hold Time DI Hold Time Relative to SK Relative to SK Relative to SK ns ns ns tPD1 Output Delay to `1' AC Test ns tPD0 Output Delay to `0' AC Test ns tSV CS to Status Valid AC Test ns tDF CS to DO in High Impedance AC Test CS = VIL ns ms ms tWP Write Cycle Time 2-82 AT93C46A AT93C46A Instruction Set for the AT93C46A Address Instruction READ EWEN ERASE WRITE ERAL WRAL EWDS SB 1 1 1 1 1 1 1 Op Code 10 00 11 01 00 00 00 x 16 A5 - A0 11XXXX A5 - A0 A5 - A0 10XXXX 01XXXX 00XXXX Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Erase memory location An - A0. Writes memory location An - A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. Writes all memory locations. Valid only at VCC = 4.5V to 5.5V. Disables all programming instructions. 2-83 Functional Description The AT93C46A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic `1') followed by the appropriate Op Code and the desired memory Address location. READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic `0') precedes the 16 bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the Erase/Write Enable state, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical `1' state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the READY / BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic `1' at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into the specified memory location. The self-timed programming cycle starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic `0' at DO indicates that programming is still in progress. A logic `1' indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic `1' state and is primarily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. Timing Diagrams Synchronous Data Timing Note: 1. This is the minimum SK period. (continued) 2-84 AT93C46A AT93C46A Organization Key for Timing Diagrams AT93C46A I/O AN DN x 16 A5 D15 Timing Diagrams (Continued) READ Timing EWEN Timing (1) Note: 1. Requires a minimum of nine clock cycles. EWDS Timing (1) Note: 1. Requires a minimum of nine clock cycles. (continued) 2-85 Timing Diagrams (Continued) WRITE Timing WRAL Timing (1, 2) Notes: 1. Valid only at VCC = 4.5V to 5.5V. 2. Requires a minimum of nine clock cycles. ERASE Timing (continued) 2-86 AT93C46A AT93C46A Timing Diagrams (Continued) TERAL Timing (1) Note: 1. Valid only at VCC = 4.5V to 5.5V. 2-87 Ordering Information tWP (max) (ms) 10 10 10 10 10 10 ICC (max) (A) 2000 800 600 2000 800 600 ISB (max) (A) 50.0 20.0 20.0 50.0 20.0 20.0 fMAX (kHz) 2000 1000 500 2000 1000 500 Ordering Code AT93C46A-10PC AT93C46A-10SC AT93C46A-10PC-2.7 AT93C46A-10SC-2.7 AT93C46A-10PC-2.5 AT93C46A-10SC-2.5 AT93C46A-10PI AT93C46A-10SI AT93C46A-10PI-2.7 AT93C46A-10SI-2.7 AT93C46A-10PI-2.5 AT93C46A-10SI-2.5 Package 8P3 8S1 8P3 8S1 8P3 8S1 8P3 8S1 8P3 8S1 8P3 8S1 Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Package Type 8P3 8S1 8 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8 Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options Blank -2.7 -2.5 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (2.5V to 5.5V) Low Voltage (1.8V to 5.5V) 2-88 AT93C46A |
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